Soft Error Detector
EDA tool for Soft Error Analysis at cell-level
TFIT® (Transistor Failure In Time) is a best-in-class transistor/cell level soft error simulator. Thanks to its unique approach and close collaboration with foundries, TFIT enables high-speed, accurate simulation of the radiation effects of standard cells and custom designs implemented in main process nodes available on the market.
The TFIT methodology is based on foundry provided characterization models of ionizing particles for each technology node. TFIT innovative algorithms lean on these foundry models to simulate radiation effects accurately at the spice level up to 100X faster than TCAD based solutions.
TFIT makes it easy to:
The TFIT models offer the basics for handling soft error rate calculations for the following environments:
IROC is partnering with major foundries and offers many foundry approved TFIT models from main stream process nodes are available.
Available TFIT Models
65, 40g, 28xx, 16FF, N10, N7, N5, N3
32nm, 28nm, 14nm, 10nm, 7nm
40xx, 40xx, 22FDX
In addition to the target technology, TFIT requires the Spice netlist and the GDS files of the analyzed design. TFIT detects the various logical states of the input design and performs the requested analysis on each of these states.
In addition to a log file containing Soft Error Rate (SER) details, TFIT outputs the sensitivity maps showing sensitive zones of the design as a function of Linear Energy Transfer. This can be helpful for understanding and optimizing sensitivity.
TFIT offers rich features covering a wide variety of applications requiring good or high levels of reliability. This is detailed in the table on the right:
Access to a standard spice simulator supporting simulation technology is mandatory to use TFIT. The following commercial simulators are supported:
Other Spice simulators could be supported upon request.
Single particle impact
< 1 minute
SEU Neutron FIT
~ 5 minutes
~ 5 minutes
~ 30 minutes