Our Soft Error Tools
- TFIT cell level — Soft error simulation tool at transistor level for library designers more
- SOCFIT circuit level — Soft error simulation tool at circuit level for chip architect more
Articles- Are Chips Getting More Reliable?
Articles- Computing Now – Are Our Electronic Circuits Getting Older?
Events- TSMC OIP 2015
Press- Grenoble Comes to San Francisco
Events- Paper co authored with Freescale at SELSE 2015
Press- ELESIS Project