IROC Technologies’ TFIT® now integrated with Siemens EDA Flow – See us at DAC 2025!
We’re proud to announce that IROC’s TFIT, our high-speed transistor-level soft error simulator, is now seamlessly integrated into Siemens Calibre LVS flow! This collaboration combines IROC’s solution with Siemens’ industry-leading tools bringing a faster, more automated, and more accurate way to simulate radiation effects at the transistor level, and helping our customers tackle reliability challenges in today’s most advanced semiconductor designs.
The presentation tile is: Enhance Your Soft Error Simulations: IROC TFIT® Now Seamlessly Integrates with Calibre® LVS
Join us at DAC 2025!
Don’t miss Samar Abdel-hady and Maximilien Glorieux presenting this collaboration at the Siemens booth #2611 on Wednesday, June 25 at 10 AM to learn how this integration accelerates radiation effects analysis.
Key Higlights:
- 100X faster than traditional TCAD radiation analysis
- Seamless workflow with automatic transistor data extraction
- Support for GDSII, OASIS, and CIF formats
- Validated accuracy matching Calibre LVS results
By integrating IROC’s TFIT solution with Siemens’ Calibre LVS environment, we’re demonstrating how industry collaboration leads to smarter, more robust EDA solutions for chip designers.
