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SHARC-FIN Tapeout Successful!

We are very pleased to announce that our FinFET SHARC-FIN ASIC has been successfully taped-out and it’s currently in manufacturing.

SHARC-FIN stands for SEE Hardening And Radiation Characterization of FINfet Technologies and it’s a complete solution for the study of Single Event Effects (SEE) in advanced processes. The chip embeds advanced test structures for memory, combinatorial and sequential cells and other complex IPs, including a Programmable Delta-Sigma Fractional PLL from Silicon Creations.

This work has been supported by the European Space Agency under ESA Contract No. 4000128352/19/NL/GLC “Definition of Radiation Effects Mitigation Techniques for Ultra-Deep Submicron Technologies” and intends to assess the suitability of Ultra Deep Submicron (UDSM) technology nodes below 22nm for space applications.

The design team was led by Dr. Maximilien GLORIEUX, IROC’s Chief Technical Officer. We thank our colleagues at TSMC, Siemens, IMEC and Silicon Creations for their excellent support and partnership.