« We benchmarked TFIT with results of tests on silicon for several designs and other tools. The correlation between the simulation results and test is impressive for this particular process node [TSMC 40nm]. Cisco is committed to continue our correlation work with TFIT on the other Si technology nodes. TFIT stands as one of the best commercially available simulation tool offered to the industry for soft error simulation.”…
« “TSMC chose IROC for SER test and simulation to provide customer needs from cell/lib SER assessment, to IC SER simulation and design optimization. IROC accurately correlates with TSMC process technology, leading to unique 40nm and 28nm SER solutions and services for TSMC customers.”
« SOCFIT is a comprehensive tool which solves the complexity of analyzing reliability issues on very large SoC designs. The complexity of the problem is that many sources of errors can affect chip reliability. SOCFIT helps quantify these issues and points to the areas of the design that need to be improved. The tool is helpful to explain the reliability performances of our design to our customer in a clear and quantitative way.