TECHNICAL DETAILS

The following technical details apply to build the test plan of a test project and define the reporting of the test.

Errors detected:

The table below shows the different type of errors detected per type of device:
  SRAM DRAM TCAM FPGA SoC FF
SEU X X X X X X
MBU/MCU X X X X X X
SEL X   X X X X
SEFI X X X   X X
Snapback X   X   X X
Tref change   X        
LUT       X    
Configuration memory       X    
Search Mode errors     X      

Tested Test Conditions per chip type:
  SRAM DRAM TCAM FPGA NVRAM Test Chip SoC FF
Vdd X X X X X X X X
Pattern X X X X X X X X
Algorithm Mode X X X X X X X X
Clock Frequency X X X X X X X X
Clock State           X X X
Temperature X X X X X X X X
Incidence Angle X X X X X X X X
ECC Activation [1]   X X X   X X  
Refresh Interval   X            
Voltage Regulator Bypass [1] X X X X X X X X
Back Bias Voltage           X    
Data Burst Length [1] X X X X X X    
[1]: When available

Vdd

The Vdd values that are considered in a test are generally the minimum, maximum and nominal Vdd values which apply to the chip. Any customer-defined value may be considered in a general way.

Pattern

This applies to memorizing structures (memories and sequential logic).Four options may be considered here:
All-0, All-1
Logical Checker Board (LCHB)
Physical Checker Board (PCHB)

Algorithm mode

Two modes can be considered here:
Static Mode
Dynamic Mode

Clock Frequency

The clock frequency can vary (two possible values: high and low) within the test conditions. Limitation of the high clock frequency are:
Test execution constraints (e.g. Speed limitation due to test equipment)
Chip use limitations (e.g. Case of prototype chip)

Clock State

This item allows making the chip clock state vary during irradiation (HIGH or LOW)

Temperature

Different temperature values may be considered in a test service.
Two temperature values can be considered:
Room Temperature
High Temperature (A 125° Celsius max)

Incidence Angle

Two angle values may be considered: 0° and 180°
iRoC may provide intermediate angle values, based on a 45° step value on demand.

ECC Activation

When testing a chip which integrates an Error Correcting Code (ECC) mechanism, chip is tested with and/or without ECC activated.

Refresh time

Applicable to DRAM, this parameter varies under radiation to study how it impacts the DRAM chip sensitivity to SE effects.

Internal Voltage Regulator Bypass

To reach a wider range of Vdd values than with the regulator on. This represents a superset of Vdd values which would be considered in standard mode.

Back Bias Voltage

Some chips may allow modifying the transistor polarization using back bias capability. In such case, iRoC can consider several polarization values (i.e. Impact flip time) and measure hence the impact of this parameter on the SE chip sensitivity.

Data Burst Length

The length of data written while using a chip may be considered as a specific test parameter. This allows seeing how the write data length impacts the chip sensitivity to SE effects.

Specific functionalities

For some complex chips, specific functions will be run by the chip when put under radiation. Observable modes of failures will then be translated into types of errors.Customer is largely involved in the definitions, implementation and analysis of results for this test condition.