SoCFIT(TM) 2.0
System Level Soft Error Analysis
Assess Your Soft Error Risk During Design
OVERVIEW
SoCFIT provides designers the means to assess the soft error risk in their System-on Chip designs early in the design flow by calculating the FIT (Failure in Time) rate for the entire design or for a specific design block. Using the SoCFIT software and models provided by iRoC, designers can quickly quantify the soft error sensitivity of different memory blocks, logic elements (considering both sequential and combinational logic) and custom IP blocks. Furthermore, they can pinpoint which areas of the design contribute mostly to the FIT. This accurate detection analysis allows designers to implement modifications effectively to reduce soft error sensitivity and therefore, enhance the reliability of their design.
SoCFIT IN THE DESIGN FLOW
Using SoCFIT with internal or external soft error models for the used library allows designers to assess the FIT rate (Failure in Time) of SoC designs.
This fast simulation tool pinpoints the areas to be fixed in order to meet the targeted FIT rate.
SoCFIT takes design description (netlist level plus as SDF timing information) and the various user defined input parameters (process library, operating frequency, and radiation environment) as inputs. From there, SoCFIT calculates the FIT rate of the total chip including logic and memory blocks. The output of the tool is the FIT rate for the elements selected (block up to full chip) in either a graphical or tabular format. SoCFIT supports both stand-alone and Cadence First EncounterTM execution environments.
KEY ANALYSIS TO DEFINE THE BEST PROTECTION OF SoC
Depending on the soft error sensitivity shown by the target block, user can elect to modify the design in order to reduce the effect of soft error if needed for the target application. The tool can be used to run fast trade-offs to determine the best mitigation technique.
