EDA Tools
Soft Errors affect transistors, but their effects are visible only at the system level with sometimes catastrophic consequences.
It is therefore important to be able to understand the real cause of failures, to diagnose it and to design accordingly. All these actions need simulation tools to be carried out.
iRoC develops two levels of analysis and simulation tools to help the industry:
- TFIT, a cell and transistor level error analyzer and optimizer. This tool is design for IP and libraries developers and foundries.
- SoCFIT, a gate level netlist error analyzer and optimizer. This tool is design for System houses and fabless companies.
TFIT, SoCFIT and our database of simulation and test results are linked to each other following the semiconductor value chain.
