Design Services/EDA TOOLS
For companies preparing their next design in 90nm technologies or smaller: Soft error is part of your design issues, and should be addressed now.
You don't need to acquire all the knowledge, iRoC as a third party specialist shares with you the best experience, skills and EDA tools the industry can buy. We customize to your need a package of service and EDA tools including :
Your best first step to solve the problem and come up to speed: contact us
We offer a bundle of solutions that:
- Assist your design team analyze Soft Error impact on IC design performances.
- Help establish and budget early Soft Error protection strategies.
- Use our design methodologies to implement cost-effective soft error protection.
- Characterize for Soft Error Rate full libraries in timely manner.
- Test Silicon to SER and latch-up.
(click on buttons on the image below for more info)

Why adopt iRoC Technologies design services?
Case Study: SoC design to meet SER specification.
"SEU FIT rate per device have to be less than 200 per device. This will have to be demonstrated on silicon through radiation test".
This is what your design team received as an additional specification for your new design in Networking, Automotive or Medical applications in 65nm. What is this SEU FIT rate and how will your team guarantee that your design will pass the test without extra cost and reducing the performance?
iRoC Design Service consultants will team up with your design engineers to achieve the most cost effective compliance to this spec.
The result will be a full compliance to the spec at first silicon, with no need of respin and minimum efforts to invest to bring the design team up to speed on SEU analysis and on a level of maturity for communication to your customer on the topic.
This cooperation will result in a design win
over
main competitors and an enhanced customer satisfaction.
In summary our the value proposition of our
design
service is:
|
FIT rate assessment at all design phase |
|
| |
|
|
FIT rate optimization at layout with identification of hot spots and trade-offs options. |
|
|
Device qualification through SER testing compliant to most advanced standards. |

