Design Services

For companies preparing their next design in 90nm technologies or lower: Soft error is part of your design issues, and should be addressed now..

You don't need to acquire all the knowledge in house, iRoC as a third party specialist shares with you the best experience, skills and tools the industry can buy. We customize for you need a package including TCAD analysis of design, definition of test chips, test services, integration of results in a customized analysis tools.

SEU requirement: cost to comply

Your best first step to solve the problem and come up to speed: contact us.

We offer a bundle of services that:

  • Assist your design team analyze Soft Error and Latch Up impact on IC design performances.
  • Help establish and budget early Soft Error protection strategy.
  • Use our design methodologies to implement cost-effective soft error protection.
  • Characterize full libraries in timely manner.
  • Test Silicon to SER and latch-up.

Why adopt iRoC Technologies design services?

Case Study: SoC design to meet SER specification.

"SEU FIT rate per device have to be less than 200 per device. This will have to be demonstrated on silicon through radiation test".

This is what your design team received as an additional specification for your new design in Networking, Automotive or Medical applications in 90nm. What is this SEU FIT rate and how your team will guarantee your design will pass the test without extra cost and reducing the performance?

iRoC Design Service consultants will team up with your design engineers to achieve the most cost effective compliance to this spec:

The result will be a full compliance to the spec at first silicon, with no need of respin and minimum efforts to invest to bring the design team up to speed on SEU analysis and a level of maturity for communication to your customer on the topic.

This cooperation will result in a design win over the team's main competitors and an enhanced customer satisfaction.

FIT rate assessment at all design phase versus libraries utilized.

FIT rate protection with innovative design architectures.

FIT rate optimization at layout with identification of hot spots and trade-offs options.

Device qualification thru SER testing compliant to most advanced standards.