Want to know about Soft Errors?
What are Soft Errors?
Soft errors are transient faults that occur in VLSI circuits due to external radiation and affect the logic states of sensitive nodes. They generally occur from nuclear decay of packaging materials or atmospheric particles accelerated towards the earth by cosmic rays.Back to the top
Why is soft error a major concern?
Neutron radiation interferes with charges held in sensitive nodes in circuits causing soft errors - or SEU (Single event upset) and they generally affect storage elements such as memory, latches and registers. Logic cores and FPGAs are known to be much less sensitive to soft errors than memories but the operating frequency increase, the geometry shrinking and the power supply reduction tend to drastically raise the soft error sensitivity of these devices.Back to the top
Why is the next generation of IC more prone to soft errors?
Due to aggressive scaling down of the power supply voltage (Vdd) and the reduction in the minimum feature size, the sensitivity of a circuit to single event upset increases. Vdd is the main sensitivity factor, decreasing the node charge to a critical level. High clock rates foster soft error vulnerability in logic parts: the probability to latch a single event upset is becoming more and more significant.Back to the top
How are soft errors measured?
The metric for soft errors is well defined. A FIT (failure in time) is one soft error for 10e9 hours / device. Recent radiation tests have shown that for a 1Gb memory in 0.25µm, the current average for Soft Error Rate (SER) is one error per week. With 0.13µm, usual memory specifications require a design under 1000 FIT : with 50 devices, this specification means 1 error per week again. Radiation tests must be performed to get accurate data for an IC SER sensitivity. For more info on our radiation testing service visit us at www.sertest.com.Back to the top
What are the practical ways to protect a chip?
To quantify the sensitivity of chips to soft errors, chip manufacturers can run radiation testing on their latest IC products. The next step would be to estimate the soft error rate during the design cycle in order to reduce soft error sensitivity before sending chips to production. But tests and estimates are not enough for chip designers, they will have to protect the designs against soft errors. We have to implement protection techniques like ECC and other efficient solutions to ensure an acceptable level of robustness against soft errors.Back to the top
What are the most common soft error effects on Integrated circuits?
The table below gives an overview of the types of errors expected per type of device.
| System Testing | Real-Time | Accelerated | |
| SEU | Yes | Yes | Yes |
| MBU/MCU | Yes | Yes | Yes |
| SEL | Yes | Yes (*) | Yes |
| SEFI | Yes (*) | Yes | |
| Snapback | Yes |
SEU: Single Event Upset
MBU/MCU: Multi Bit Upset/Multi Cell Upset
SEL: Single Event Latch Up
SEFI: Single Event Failure Interrupt
For the exact definition of all these terms, please refer to Jedec Standard.Back to the top