Technical Publications and Papers
You will find here a very exhaustive list of white papers on the topic of Soft Errors.
Abstracts are included. If you would like a full paper, please contact us with the reference of the document.
TFIT related papers
SoCFIT related papers
Other conferences papers
TFIT related papers
MEASUREMENT OF NEUTRON-INDUCED SINGLE EVENT TRANSIENT PULSE WIDTH PULSE NARROWER THAN 100ps
Abstract: A novel SET pulse measurement circuit is proposed which can detect pulses narrower than 100ps. Alternation of SET pulses during the propagation through the chain of target cells is minimized, which is attributed to small chain length (typically 20). This circuit configuration contributes to obtaining pulse distribution similar to that observed in actual circuit in use. Distribution of SET pulse width measured by our circuit through the white neutron beam testing agrees well with that estimated by computer simulation.
STUDY ON INFLUENCE OF DEVICE STRUCTURE DIMENSIONS AND PROFILES ON CHARGE COLLECTION CURRENT CAUSING SER PULSE LEADING TO SOFT ERROR IN LOGIC CIRCUITS
Abstract: Current responses due to the strike of ionized particle onto nMOS transistor of 90nm and 55nm generation have been analyzed through 3D device simulations. From the current response, duration of charge collection (tcc) is determined, which correlated strongly with the width of erroneous pulse (SET pulse). Causes of the difference between tcc values of 90nm and 55nm generation MOSFETs have been investigated and it is found that the difference in STI depth and width of p-well contact line between these two generations influences tcc mainly. This is because that the resistance below the p-well contact affects the ability to pull out the excess holes remaining in the channel region. It is also shown that there is room for reducing tcc and hence SET pulse width by well profile engineering.
SoCFIT related papers
A MULTI-PARTNER SOFT ERROR RATE ANALYSIS OF AN INFINIBAND HOST CHANNEL ADAPTER
Abstract: We present the results of a Soft Error Rate (SER) analysis flow performed on a high-performance, commercial InfiniBand Host Channel Adapter. The primary goals of this evaluation consist in characterizing the device reliability from a SER perspective exhaustively, taking into account all the factors affecting the SER sensitivity in a systematic approach. This method consequently helps the designers implementing the optimal error mitigation methodology. The work presented in this paper follow a practical, systematical method that takes into account the important stages of the design flow from the SER figures of the standard cell library to SER-related field problems. Moreover, this project represented the opportunity to reunite in a common framework the technology provider, the chip designers and the SER-solutions provider. In addition, field data show no contradiction to the predicted results and an evolution of the SER analysis for the next generation of the device has been scheduled.
Other conferences papers
A SYNTHETIC SOFT ERROR RATE SIMULATION CONSIDERING NEUTRON-INDUCED SINGLE EVENT TRANSIENT FROM TRANSISTOR TO LSI-CHIP LEVEL
Abstract: Soft Error phenomena induced by the Sea-level cosmic neutron have been investigated by using a simulation system that covers from an individual MOSFET device level to an LSI-chip level.This system consists of several kinds of simulations codes tools, such as mixed-mode 3D device simulator, SPICE circuit simulator and analysis tools of gate-levels net-lists. A comprehensive practical simulation flow is demonstrated in this paper on commercial 90 nm generation logic devices and standard cells.
A VARIATION OF SRAM ALPHA-INDUCED SOFT ERROR RATE WITH TECHOLOGY NODE
Abstract: this document presents a compilation of results from tests performed by iRoC Technologies on SER induced by alpha particles on SRAM memories for technology nodes from 180nm to 65 nm. The aim of this study is to establish the variation of sensitivity with technology node for SEU and MCU and to analyze the possible influence of different designs and technological parameters at a given technology node.
A SYSTEMATICAL METHOD OF QUANTIFYING SEU FIT
Abstract:
We
present a practical, systematical method for the
evaluation of the Soft Error Rate (SER) of
microelectronic devices. Existing methodologies,
practices and tools are integrated in a common
approach while highlighting the need for specific data
or tools. The showcased method is particularly
adapted for evaluating the SER of very complex
microelectronic devices by engineers confronted to
increasingly demanding reliability requirements.
A LOW-COST SINGLE-EVENT LATCHUP MITIGATION SCHEME
Abstract: Single-event latchup is one of the most threatening single event effects as the induced current may destroy the affected device. Existing latchup mitigation schemes may induce a very high area cost or may require modifying the fabrication process. In this paper we present a new single-event latchup mitigation approach implemented at design level that protects devices from destruction and preserve circuit state at very low area cost.
Characterizing Laser-Induced Pulses in ICs: Methodology and Results
Abstract: Like other silicon integrated circuit (IC) domains, the smart card market is very competitive and main actors are constantly trying to design the cheapest and safest circuits to ensure their consumers' satisfaction. These specificities lead smart cards actors to design standard cell-based tamper resistant ICs and to characterize their circuits' sensitivity.
In this paper, we present some experimental results aimed at characterizing the sensitivity to laser-induced transient pulses (and their duration) of elementary cells from the 0,13 μm standard cell library STM HCMOS9GP. They were obtained for a specially designed and fabricated experimental circuit. The data obtained here allow us for better understanding of laser attacks and would be used to design integrated circuits with better protection against such attacks. The final goal of this work is to build and augment new simulation models dedicated to laser-induced faults aimed specifically at smart card industry.
IRPS 06 (accepted)
Abstract: Measurement of soft error rates (SER) of ten commercial SRAMs of 0.35 μm to 90 nm technologies have been completed at the ILL thermal neutron facility. Results establish the sensitivity of old and recent SRAMs showing the impact of 10B concentrations in BPSG and p-type regions. 10B results are also compared to high-energy neutron SER. [Keywords: soft error, single-event upset (SEU), thermal neutrons, cross-section, boron].
Cancer-Radiotherapy
Equipment as a Cause of
Soft Errors in Electronic Equipment (IEEE, Wilkinson and all, Sep 2005)
Abstract:The undesirable production of secondary
neutrons by cancer-radiotherapy linear accelerators (linac) has been
demonstrated to cause soft errors in nearby electronics through the 10B(n,
a)7Li reaction. 10B is a component in the BPSG
used as a dielectric material in some integrated-circuit (IC)
fabrication processes.
Modeling of Transients Caused by a Laser Attack on Smart Cards
Abstract:
Several
techniques for
extracting data from smart cards have been described in the literature,
including the so called differential fault analysis (DFA) that relies
on perturbing
the chip operations to deduce the data. In this paper, we present some
experimental results of the DFA that relies on using a laser beam.
Robust
System
Design with Built-In Soft-Error Resilience (IEEE, Intel-iRoC, Feb 2005)
Abstract: Transient errors caused by terrestrial
radiation pose a major barrier to robust system design. A system’s
susceptibility to such errors increases in advanced technologies,
making the incorporation of effective protection mechanisms into chip
designs essential. A new design paradigm reuses design-for-testability
and debug resources to eliminate such errors
As nanometer processes are adopted, reliability has once again become one of the hottest semiconductor topics. Among reliability failure mechanisms, soft errors are becoming the biggest cause of failures in-the-field. By striking device transistors, alpha particles and atmospheric neutrons can cause unpredictable bit flips called soft errors. While a phenomena that has been around forever, it has become a general market issue as activation energies drop and the amount of SRAM memory embedded in new chip generations explodes. The iRoC Technologies paper will detail ways of evaluating the SER threat, and will present new techniques and design tips for overcoming technology obstacles and achieving highly reliable ICs.
New Trends in the Soft Error Threat
Reliability is one of the major concerns for advanced semi-conductor manufacturers. Soft errors induced by alpha particles and atmospheric neutrons are among these concerns. By hitting the transistors, such particles may cause unpredictable bit flips in ICs (integrated circuit). This effect is becoming more and more preeminent as the industry moves along the technology roadmap to smaller, more sensitive technologies. To quantify the sensitivity of their chips to soft errors, it is necessary for chip manufacturers to run radiation testing on their latest IC generation
Design for Soft-Error Robustness To Rescue Deep Submicron Scaling
Progress in technological scaling allows the integration into a single chip of hundreds of millions of transistors, moving quickly to the multi-billion transistor capacities. The integration of complex systems into a single chip, that may include heterogeneous parts such as logic, SRAM, DRAM non-volatile memories, analog and even micromechanical and optical parts, is becoming a reality
VDSM IC Logic and Memory Signal Integrity and Soft Errors
Due to the VDSM evolution and an electronic systems market moving at a neck-breaking speed, the semiconductor industry is facing exciting new challenges all the time. As minimum layout dimensions continue to shrink and correspondingly the number of functions that can be put on a SoC continues to grow, signal integrity is becoming a major issue. Some of the growing effects are the so-called “transient errors” which are due to temporary conditions of use and the environment
Embedded Robustness IPs for transient error free ICs
Shrinking process geometries will make it imperative for designers to start paying attention to transient-error protection. Self-correcting intelligence embedded in ICs protects electronic systems against such unpredictable and insidious errors. Infrastructure IPs that focus on transient faults are a leading type of self-correcting intelligence
Single Event Effect in Avionics
The occurrence of single event upset (SEU) in aircraft electronics has evolved from a series of interesting anecdotal incidents to accepted fact. A study completed in 1992 demonstrated that SEUs are real, that the measured in-flight rates correlate with the atmospheric neutron flux, and that the rates can be calculated using laboratory SEU data. Once avionics SEU was shown to be an actual effect, it had to be dealt with in avionics designs
Single Event Upset at Ground Level
Ground level upsets have been observed in computer systems containing large amounts of random access memory (RAM). Atmospheric neutrons are most likely the major cause of the upsets based on measured data using the Weapons Neutron Research (WNR) neutron beam
Latent Damage in CMOS Devices From Single-Event Latchup
Permanent damage effects are studied for several types of CMOS circuits that are sensitive to single-event latchup. The emphasis is placed on latent damage effects, where devices remained functional despite significant structural damage to their interconnects. This type of damage was observed during latchup testing with both laser pulses and heavy ions. Microscopic examination of the damaged regions after latchup testing revealed small metallic spheres and cracked, voided interconnects
Neutron Induced Latchup in SRAMs at Ground Level
Neutron-induced single-event latchup has been studied in SRAMs manufactured by several different vendors. These SRAMs span different cell designs (six-transistor and four-transistor cells), technology generations (0.25 µm to 0.14 µm) and power supplies (5 V to 1.5 V). While some technologies appear to be latchup-free in neutron environments, others have neutron-induced latchup failure-in-time (FIT) rates as high as 300 FIT/Mbit at room temperature and maximum rated voltage. Latchup FIT rates increase dramatically with temperature. The observed latchup rates can lead to very high failure rates in systems with large amounts of memory, and can’t be circumvented using error correction
Microbeam mapping of single event latchups and single event upsets in CMOS SRAMS
The first simultaneous microbeam mapping of single event upset (SEU) and latchup (SEL) in the CMOS RAM HM65162 is presented. We found that the shapes of the sensitive areas depend on VDD, on the ions being used and on the site on the chip being hit by the ion. In particular, we found SEL sensitive sites close to the main power supply lines between the memory-bit-arrays by detecting the accompanying current surge. All these SELs were also accompanied by bit-flips elsewhere in the memory (which we call `indirect' SEUs in contrast to the well known SEUs induced in the hit memory cell only). When identical SEL sensitive sites were hit farther away from the supply lines only